

Processes | |
| PROCESS_17 | ( clk , clr_cnt , rst ) |
Signals | |
| count2 | std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' ) |
| PROCESS_17 | ( clk , | |
| clr_cnt , | ||
| rst ) |
count2 std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' ) [Signal] |
1.6.2-20100208