rtl Architecture Reference
Inheritance diagram for rtl:
Collaboration diagram for rtl:
Processes | |
| fsm | ( clk , rstb ) |
| counter | ( clk , rstb ) |
| address | ( clk , rstb ) |
| data_strobe | ( clk , rstb ) |
Types | |
| state_t | ( idle , mem_read , last_mem_cycle , last_dstb_trans , close_trans , close_trans_en ) |
Signals | |
| st_i | state_t |
| cnt_clr_i | std_logic |
| cnt_i | unsigned ( 8 downto 0 ) |
| dstb_en_i | std_logic |
| dstb_i | std_logic |
| max_i | integer |
Member Function Documentation
| address | ( clk , | |
| rstb ) |
| counter | ( clk , | |
| rstb ) |
| data_strobe | ( clk , | |
| rstb ) |
| fsm | ( clk , | |
| rstb ) |
Member Data Documentation
cnt_clr_i std_logic [Signal] |
cnt_i unsigned ( 8 downto 0 ) [Signal] |
dstb_en_i std_logic [Signal] |
dstb_i std_logic [Signal] |
max_i integer [Signal] |
state_t ( idle , mem_read , last_mem_cycle , last_dstb_trans , close_trans , close_trans_en ) [Type] |
The documentation for this class was generated from the following file:
- bc/bc_core/tsm_man/mem_rdo/mem_rdo.vhd
