Architectures | |
rtl | Architecture |
Libraries | |
ieee | |
Packages | |
std_logic_1164 | |
numeric_std | |
Generics | |
TIMES | integer range 2 to 8 := 3 |
WIDTH | natural := 10 |
OVER | boolean := true |
AUTO | boolean := true |
Ports | |
clk | in std_logic |
rstb | in std_logic |
rst | in std_logic |
enable | in std_logic |
value | in std_logic_vector ( width-1 downto 0 ) |
threshold | in std_logic_vector ( width-1 downto 0 ) |
int | out std_logic |
AUTO boolean := true [Generic] |
clk in std_logic [Port] |
enable in std_logic [Port] |
ieee library [Library] |
int out std_logic [Port] |
numeric_std package [Package] |
OVER boolean := true [Generic] |
rst in std_logic [Port] |
rstb in std_logic [Port] |
std_logic_1164 package [Package] |
threshold in std_logic_vector ( width-1 downto 0 ) [Port] |
TIMES integer range 2 to 8 := 3 [Generic] |
value in std_logic_vector ( width-1 downto 0 ) [Port] |
WIDTH natural := 10 [Generic] |