rtl Architecture Reference

Inheritance diagram for rtl:

[legend]

Collaboration diagram for rtl:

[legend]

List of all members.

Processes
shift_it	( clk , rstb )
Signals
al_evl_or_i	std_logic
chrd_st_i	std_logic
next_ch_i	std_logic
accept_i	std_logic
shift_in_i	std_logic
shift_en_i	std_logic
ch_cnt_i	std_logic_vector ( 6 downto 0 )
parity_i	std_logic
result_i	std_logic_vector ( 33 downto 0 )
evl_reg_i	std_logic_vector ( 127 downto 0 )
Component Instantiations
ch_cnt	ch_counter <Entity ch_counter>
read_it	read_evl <Entity read_evl>
transfer	evlreg_trsf <Entity evlreg_trsf>

---

Member Function Documentation

[Process]

shift_it		( clk ,
		rstb )

---

Member Data Documentation

accept_i std_logic [Signal]

al_evl_or_i std_logic [Signal]

ch_cnt ch_counter [Component Instantiation]

ch_cnt_i std_logic_vector ( 6 downto 0 ) [Signal]

chrd_st_i std_logic [Signal]

evl_reg_i std_logic_vector ( 127 downto 0 ) [Signal]

next_ch_i std_logic [Signal]

parity_i std_logic [Signal]

read_it read_evl [Component Instantiation]

result_i std_logic_vector ( 33 downto 0 ) [Signal]

shift_en_i std_logic [Signal]

shift_in_i std_logic [Signal]

transfer evlreg_trsf [Component Instantiation]

---

The documentation for this class was generated from the following file:

• bc/bc_core/evl_man/evl_man.vhd