rtl Architecture Reference
Inheritance diagram for rtl:
Collaboration diagram for rtl:
Processes | |
| next_state | ( clk , rstb ) |
| fsm | ( st_i , al_trsf ) |
| output | ( clk , rstb ) |
| counter | ( dstb , clear_i , rstb ) |
Types | |
| state | ( s0 , s1 , s2 , s3 ) |
Signals | |
| st_i | state |
| nx_st_i | state |
| enable_i | std_logic |
| clear_i | std_logic |
| cnt_i | unsigned ( 7 downto 0 ) |
Member Function Documentation
| counter | ( dstb , | |
| clear_i , | ||
| rstb ) |
| fsm | ( st_i , | |
| al_trsf ) |
| next_state | ( clk , | |
| rstb ) |
| output | ( clk , | |
| rstb ) |
Member Data Documentation
clear_i std_logic [Signal] |
cnt_i unsigned ( 7 downto 0 ) [Signal] |
enable_i std_logic [Signal] |
state ( s0 , s1 , s2 , s3 ) [Type] |
The documentation for this class was generated from the following file:
- bc/bc_core/registers/counters/dstb_counter/dstb_counter.vhd
