ack_i | rtl5 | [Signal] |
clk_gen(clk, rstb) | rtl5 | [Process] |
clk_i | rtl5 | [Signal] |
cnt_i | rtl5 | [Signal] |
div_store_i | rtl5 | [Signal] |
idx_i | rtl5 | [Signal] |
max_i | rtl5 | [Signal] |
new_values_i | rtl5 | [Signal] |
NPHASES | rtl5 | [Constant] |
phase_gen(clk) | rtl5 | [Process] |
phase_store_i | rtl5 | [Signal] |
phases_i | rtl5 | [Signal] |
store_values(clk, rstb) | rtl5 | [Process] |
sync_i | rtl5 | [Signal] |
sync_ii | rtl5 | [Signal] |