Architectures | |
rtl | Architecture |
Libraries | |
ieee | |
Packages | |
std_logic_1164 | |
Generics | |
WIDTH | integer := 1 |
Ports | |
cds_alias_sig1 | in std_logic_vector ( width downto 1 ) |
cds_alias_sig2 | in std_logic_vector ( width downto 1 ) |
Cadence alias entity
cds_alias_sig1 in std_logic_vector ( width downto 1 ) [Port] |
cds_alias_sig2 in std_logic_vector ( width downto 1 ) [Port] |
ieee library [Library] |
std_logic_1164 package [Package] |
WIDTH integer := 1 [Generic] |