Rcu.cxx

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00001 // -*- mode: C++ -*- 
00002 //
00003 // Copyright (C) 2006 Christian Holm Christensen <cholm@nbi.dk>
00004 //
00005 // This library is free software; you can redistribute it and/or
00006 // modify it under the terms of the GNU Lesser General Public License
00007 // as published by the Free Software Foundation; either version 2.1
00008 // of the License, or (at your option) any later version.
00009 //
00010 // This library is distributed in the hope that it will be useful,
00011 // but WITHOUT ANY WARRANTY; without even the implied warranty of
00012 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00013 // Lesser General Public License for more details.
00014 //
00015 // You should have received a copy of the GNU Lesser General Public
00016 // License along with this library; if not, write to the Free
00017 // Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
00018 // 02111-1307 USA
00019 //
00025 #include "Rcu.h"
00026 #include <rcuxx/Rcu.h>
00027 #include <rcudb/Server.h>
00028 #include "SingleValue.h"
00029 #include "BlobValue.h"
00030 
00031 //____________________________________________________________________
00032 Rcuxx::RcuRegister*
00033 RcuConf::Rcu::Name2Register(const std::string& name) 
00034 {
00035   Rcuxx::RcuRegister* reg = 0;
00036   if      (name == "ERRST")     reg = 0; // Read-only fRcu.ERRST(); 
00037   else if (name == "TRCFG1")    reg = fRcu.TRCFG1(); 
00038   else if (name == "TRCNT")     reg = 0; // Read-only fRcu.TRCNT(); 
00039   else if (name == "LWADD")     reg = 0; // Read-only fRcu.LWADD(); 
00040   else if (name == "IRADD")     reg = 0; // Read-only fRcu.IRADD(); 
00041   else if (name == "IRDAT")     reg = 0; // Read-only fRcu.IRDAT(); 
00042   else if (name == "PMCFG")     reg = fRcu.PMCFG(); 
00043   else if (name == "CHADD")     reg = 0; // Read-only fRcu.CHADD(); 
00044   else if (name == "ACTFEC")    reg = fRcu.ACTFEC(); 
00045   else if (name == "RDOFEC")    reg = 0; // Read-only fRcu.RDOFEC(); 
00046   else if (name == "RESREG")    reg = 0; // Read-only fRcu.RESREG(); 
00047   else if (name == "ERRREG")    reg = 0; // Read-only fRcu.ERRREG(); 
00048   else if (name == "INTMOD")    reg = fRcu.INTMOD(); 
00049   else if (name == "SCADD")     reg = 0; // Invalid fRcu.SCADD(); 
00050   else if (name == "SCDAT")     reg = 0; // Invalid fRcu.SCDAT(); 
00051   else if (name == "FWVERS")    reg = 0; // Read-only fRcu.FWVERS(); 
00052   else if (name == "INTREG")    reg = 0; // Read-only fRcu.INTREG(); 
00053   else if (name == "EVWORD")    reg = 0; // Read-only fRcu.EVWORD(); 
00054   else if (name == "FMIREG")    reg = fRcu.FMIREG(); 
00055   else if (name == "FMOREG")    reg = fRcu.FMOREG(); 
00056   else if (name == "TRCFG2")    reg = fRcu.TRCFG2(); 
00057   std::cout << "Name2Register(\"" << name << "\") -> " << reg 
00058             << " (\"" << name << "\" == \"PMCFG\" -> " 
00059             << (name == "PMCFG") << ")" << std::endl;
00060   return reg;
00061 }
00062 
00063 //____________________________________________________________________
00064 Rcuxx::RcuCommand*
00065 RcuConf::Rcu::Name2Command(const std::string& name) 
00066 {
00067   Rcuxx::RcuCommand* cmd = 0;
00068   if      (name == "RS_STATUS") cmd = fRcu.RS_STATUS(); 
00069   else if (name == "RS_TRCFG")  cmd = fRcu.RS_TRCFG(); 
00070   else if (name == "RS_TRCNT")  cmd = fRcu.RS_TRCNT(); 
00071   else if (name == "EXEC")      cmd = fRcu.EXEC(); 
00072   else if (name == "ABORT")     cmd = 0; // Invalid fRcu.ABORT(); 
00073   else if (name == "FECRST")    cmd = fRcu.FECRST(); 
00074   else if (name == "SWTRG")     cmd = fRcu.SWTRG(); 
00075   else if (name == "RS_DMEM1")  cmd = fRcu.RS_DMEM1(); 
00076   else if (name == "RS_DMEM2")  cmd = fRcu.RS_DMEM2(); 
00077   else if (name == "DCS_ON")    cmd = fRcu.DCS_ON(); 
00078   else if (name == "DDL_ON")    cmd = fRcu.DDL_ON(); 
00079   else if (name == "L1_TTC")    cmd = fRcu.L1_TTC(); 
00080   else if (name == "L1_I2C")    cmd = fRcu.L1_I2C(); 
00081   else if (name == "L1_CMD")    cmd = fRcu.L1_CMD(); 
00082   else if (name == "GLB_RESET") cmd = fRcu.GLB_RESET(); 
00083   else if (name == "RCU_RESET") cmd = fRcu.RCU_RESET(); 
00084   else if (name == "RS_ERRREG") cmd = fRcu.RS_ERRREG(); 
00085   else if (name == "RS_RESREG") cmd = 0; // Missing fRcu.RS_RESREG(); 
00086   else if (name == "SCEXEC")    cmd = 0; // Invalid fRcu.SCEXEC(); 
00087   else if (name == "TRG_CLR")   cmd = 0; // Invalid fRcu.TRG_CLR(); 
00088   else if (name == "WRFM")      cmd = 0; // Invalid fRcu.WRFM(); 
00089   else if (name == "RDFM")      cmd = 0; // Invalid fRcu.RDFM(); 
00090   else if (name == "RDABORT")   cmd = 0; // Invalid fRcu.RDABORT(); 
00091   else if (name == "CLR_EVTAG") cmd = 0; // Invalid fRcu.CLR_EVTAG(); 
00092   else if (name == "SCCOMMAND") cmd = 0; // Invalid fRcu.SCCOMMAND(); 
00093   return cmd;
00094 }
00095 
00096 //____________________________________________________________________
00097 Rcuxx::RcuMemory*
00098 RcuConf::Rcu::Name2Memory(const std::string& name) 
00099 {
00100   Rcuxx::RcuMemory* mem = 0;
00101   if      (name == "IMEM")      mem = fRcu.IMEM();
00102   else if (name == "PMEM")      mem = fRcu.PMEM();
00103   else if (name == "RMEM")      mem = 0; // Invalid fRcu.RMEM();
00104   else if (name == "DM1")       mem = 0; // Invalid fRcu.DM1();
00105   else if (name == "DM2")       mem = 0; // Invalid fRcu.DM2();
00106   else if (name == "ACL")       mem = fRcu.ACL();
00107   else if (name == "HEADER")    mem = fRcu.HEADER();
00108   else if (name == "STATUS")    mem = 0; // Invalid fRcu.STATUS();
00109   return mem;
00110 }
00111 
00112 //____________________________________________________________________
00113 unsigned int
00114 RcuConf::Rcu::Write(const Parameter&   p, 
00115                     const SingleValue& v) 
00116 {
00117   if (p.IsBlob()) return kInvalidValue;
00118   std::cout << "Check if '" << p.Name() << "' is for us" << std::endl;
00119   
00120   // Check if this is a register 
00121   Rcuxx::RcuRegister* reg  = Name2Register(p.Name());
00122   // We return negative error codes for the Rcu++ errors. 
00123   if (reg) {
00124     std::cout << "Writing " << reg->Name() << " to Rcu" << std::endl;
00125     reg->Decode(v.Values());
00126     return - reg->Commit();
00127   }
00128   
00129   std::cout << "Check if '" << p.Name() << "' is for us" << std::endl;
00130   // Check if this is a command 
00131   Rcuxx::RcuCommand*  cmd = Name2Command(p.Name());
00132   if (cmd) {
00133     std::cout << "Writing " << cmd->Name() << " to Rcu" << std::endl;
00134     cmd->SetArgument(v.Values());
00135     return - cmd->Commit();
00136   }
00137   return kUnknownParameter;
00138 }
00139   
00140 //____________________________________________________________________
00141 unsigned int
00142 RcuConf::Rcu::Write(const Parameter&   p, 
00143                     const BlobValue&   v) 
00144 {
00145   if (!p.IsBlob()) return kInvalidValue;
00146   
00147   // Check if this is a memory
00148   Rcuxx::RcuMemory* mem = Name2Memory(p.Name());
00149   // We return negative error codes for the Rcu++ errors. 
00150   if (mem) {
00151     std::cout << "Writing " << mem->Name() << " to Rcu" << std::endl;
00152     std::vector<unsigned int> vals;
00153     v.Values(vals);
00154     mem->Set(0, vals.size(), &(vals[0]));
00155     return - mem->Commit(0, vals.size());
00156   }
00157   return kUnknownParameter;
00158 }
00159 
00160 //____________________________________________________________________
00161 unsigned int
00162 RcuConf::Rcu::Read(const Parameter&   p, 
00163                    SingleValue&       v) 
00164 {
00165   if (p.IsBlob()) return kInvalidValue;
00166   
00167   // Check if this is a register 
00168   Rcuxx::RcuRegister* reg  = Name2Register(p.Name());
00169   // We return negative error codes for the Rcu++ errors. 
00170   if (reg) {
00171     unsigned ret = reg->Update(); // Should we do this?
00172     v.Set(reg->Encode()); 
00173     return - ret;
00174   }
00175   
00176   // Check if this is a command 
00177   Rcuxx::RcuCommand*  cmd = Name2Command(p.Name());
00178   if (cmd) {
00179     // v = cmd->Argument();
00180     return kSuccess;
00181   }
00182   return kUnknownParameter;
00183 }
00184   
00185 //____________________________________________________________________
00186 unsigned int
00187 RcuConf::Rcu::Read(const Parameter&   p, 
00188                    BlobValue&         v) 
00189 {
00190   if (!p.IsBlob()) return kInvalidValue;
00191   
00192   // Check if this is a memory
00193   Rcuxx::RcuMemory* mem = Name2Memory(p.Name());
00194   // We return negative error codes for the Rcu++ errors. 
00195   if (mem) {
00196     std::vector<unsigned int> vals;
00197     unsigned int ret = mem->Update(); // Should we do this?
00198     v.Set(mem->Data()); 
00199     return ret;
00200   }
00201   return kUnknownParameter;
00202 }
00203 
00204 //____________________________________________________________________
00205 void
00206 RcuConf::Rcu::StartBlock()
00207 {
00208   std::cout << "Rcu @ " << &fRcu << std::endl;
00209   fRcu.StartBlock();
00210 }
00211 
00212 //____________________________________________________________________
00213 int
00214 RcuConf::Rcu::EndBlock()
00215 {
00216   return fRcu.EndBlock();
00217 }
00218 
00219 //____________________________________________________________________
00220 long int* 
00221 RcuConf::Rcu::GetBlock() const
00222 {
00223   const Rcuxx::Rcu::Block_t& block = fRcu.GetBlock();
00224   return const_cast<long int*>(&(block[0]));
00225 }
00226 
00227 //____________________________________________________________________
00228 const std::string&
00229 RcuConf::Rcu::ErrorString(int ret) 
00230 {
00231   return fErrorString = fRcu.ErrorString(ret);
00232 }
00233 
00234 //____________________________________________________________________
00235 bool
00236 RcuConf::Rcu::Create(RcuDb::Server& s) 
00237 {
00238   // Everything is in the RCU 
00239   Parameter::Where w = Parameter::kRcu;
00240   // Create throws an exception in case of errors
00241   try {
00242     /* === Registers === */
00243     // Component::Create(s, "ERRST",    w, false, 0x0); // Read-only
00244     Component::Create(s, "TRCFG1",      w, false, 0xffffffff);
00245     // Component::Create(s, "TRCNT",    w, false, 0x0); // Read-only
00246     // Component::Create(s, "LWADD",    w, false, 0x0); // Read-only
00247     // Component::Create(s, "IRADD",    w, false, 0x0); // Read-only
00248     // Component::Create(s, "IRDAT",    w, false, 0x0); // Read-only
00249     Component::Create(s, "PMCFG",       w, false, 0xffffffff);
00250     // Component::Create(s, "CHADD",    w, false, 0x0); // Read-only
00251     Component::Create(s, "ACTFEC",      w, false, 0xffffffff);
00252     // Component::Create(s, "RDOFEC",   w, false, 0x0); // Read-only
00253     // Component::Create(s, "RESREG",   w, false, 0x0); // Read-only
00254     // Component::Create(s, "ERRREG",   w, false, 0x0); // Read-only
00255     Component::Create(s, "INTMOD",      w, false, 0xffffffff);
00256     // Component::Create(s, "SCADD",    w, false, 0x0); // Invalid
00257     // Component::Create(s, "SCDAT",    w, false, 0x0); // Invalid
00258     // Component::Create(s, "FWVERS",   w, false, 0x0); // Read-only
00259     // Component::Create(s, "INTREG",   w, false, 0x0); // Read-only
00260     // Component::Create(s, "EVWORD",   w, false, 0x0); // Read-only
00261     // Component::Create(s, "FMIREG",   w, false, 0x0); // U2F
00262     // Component::Create(s, "FMOREG",   w, false, 0x0); // U2F
00263     //  Component::Create(s, "TRCFG2",  w, false, 0x0); // U2F
00264     /* === Commands === */
00265     Component::Create(s, "RS_STATUS",   w, false, 0xffffffff);
00266     Component::Create(s, "RS_TRCFG",    w, false, 0xffffffff);
00267     Component::Create(s, "RS_TRCNT",    w, false, 0xffffffff);
00268     Component::Create(s, "EXEC",        w, false, 0xffffffff);
00269     // Component::Create(s, "ABORT",    w, false, 0x0); // Invalid
00270     Component::Create(s, "FECRST",      w, false, 0xffffffff);
00271     Component::Create(s, "SWTRG",       w, false, 0xffffffff);
00272     Component::Create(s, "RS_DMEM1",    w, false, 0xffffffff);
00273     Component::Create(s, "RS_DMEM2",    w, false, 0xffffffff);
00274     Component::Create(s, "DCS_ON",      w, false, 0xffffffff);
00275     Component::Create(s, "DDL_ON",      w, false, 0xffffffff);
00276     Component::Create(s, "L1_TTC",      w, false, 0xffffffff);
00277     Component::Create(s, "L1_I2C",      w, false, 0xffffffff);
00278     Component::Create(s, "L1_CMD",      w, false, 0xffffffff);
00279     Component::Create(s, "GLB_RESET",   w, false, 0xffffffff);
00280     Component::Create(s, "RCU_RESET",   w, false, 0xffffffff);
00281     Component::Create(s, "RS_ERRREG",   w, false, 0xffffffff);
00282     Component::Create(s, "RS_RESREG",   w, false, 0xffffffff);
00283     // Component::Create(s, "SCEXEC",   w, false, 0x0); // Invalid
00284     Component::Create(s, "TRG_CLR",     w, false, 0xffffffff);
00285     // Component::Create(s, "WRFM",     w, false, 0x0); // U2F
00286     // Component::Create(s, "RDFM",     w, false, 0x0); // U2F
00287     // Component::Create(s, "RDABORT",  w, false, 0x0); // U2F
00288     // Component::Create(s, "CLR_EVTAG",w, false, 0x0); // U2F
00289     // Component::Create(s, "SCCOMMAND",w, false, 0x0); // Invalid
00290     /* === Memories === */
00291     Component::Create(s, "IMEM",        w, true,  0xffffffff);
00292     Component::Create(s, "PMEM",        w, true,  0xffffffff);
00293     // Component::Create(s, "RMEM",     w, false, 0x0); // Invalid
00294     // Component::Create(s, "DM1",      w, false, 0x0); // Invalid
00295     // Component::Create(s, "DM2",      w, false, 0x0); // Invalid
00296     Component::Create(s, "ACL",         w, true,  0xffffffff);
00297     Component::Create(s, "HEADER",      w, true,  0xffffffff);
00298     // Component::Create(s, "STATUS",   w, false, 0x0); // Invalid
00299   }
00300   catch (bool& e) {
00301     return e;
00302   }
00303   return true;
00304 }
00305 
00306 
00307 //____________________________________________________________________
00308 //
00309 // EOF
00310 //
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